Performance Estimation in Analog Computer Aided Design

In this paper, part of a joint effort in developing an analog design automation system with different levels of synthesis has been described. The study has been restricted to various types of analog CMOS circuits. Transistors have been modelled using analog neural networks trained with data obtained from simulation tools. Using these models in a circuit block, DC operating points have been determined iteratively and power dissipated by the circuit has been calculated in the DC analysis. In the AC analysis, gain and bandwidth of the system have been calculated, completing an evaluation cycle. Evaluation cycles have been used in a search mechanism where a range of input parameters have been swept in order to obtain the performance limits of the given circuit topology.